1. Field of the Invention
The present invention relates to a linearity enhancement circuit of a digital/analog (D/A) converter, a ΣΔ A/D converter, and a reception apparatus. More particularly, the invention relates to a linearity enhancement circuit used by an A/D converter and a D/A converter involving the use of ΣΔ modulation, such as a feedback D/A converter inside a ΣΔ A/D converter and a ΣΔ D/A converter.
2. Description of the Related Art
FIG. 1 is a block diagram showing a basic structure of a ΣΔ A/D converter. The ΣΔ A/D converter 1 is made up of a filter block 2, an A/D converter 3 with low resolution (of 1 to 5 bits), a D/A converter 4 having the same bit count as the A/D converter 3, and a subtractor 5 at the input stage. Because the ΣΔ A/D converter is a feedback-based system, the nonlinearity and noise of the circuit are reduced and high resolution is implemented thereby.
However, the closer the components of the ΣΔ A/D converter to the analog input side, the more difficult for these components to reduce the nonlinearity and noise of the circuit. For this reason, the input circuit of the filter block 2 and the D/A converter 4 are required to possess enhanced linearity and low-noise characteristics. Because the nonlinearity of the D/A converter 4 tends to raise the nose floor, it is important to guarantee the linearity of the D/A converter especially if the A/D converter in use is other than a one-bit A/D converter.
As one way to improve the linearity of the multi-bit D/A converter, there exists the technique known as data weighted averaging (called DWA hereunder) disclosed in “Linearity Enhancement of Multibit ΣΔ A/D and D/A Converters Using Data Weighted Averaging,” by Rex T. Baird and Terri S. Fiez, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING VOL. 42, NO. 12, December 1995.
FIGS. 2A and 2B are schematic views showing how a D/A converter operates without DWA and using DWA, respectively. FIGS. 2A and 2B each illustrate a three-bit D/A converter composed of seven current sources I1 through I7. Where DWA is not used, as in the case of FIG. 2A, the current sources are always used successively from left to right (i.e., starting from LSB (least significant bit)) based on DAC code. On the other hand, where DWA is used as indicated in FIG. 2B, the current source about to be used is always different from the one used immediately precedingly. Resorting to DWA makes it possible to shift the noise stemming from current source dispersion (i.e., nonlinearity) out of band to higher frequencies.
FIG. 3 is a schematic view showing a typical structure of an ordinary linearity enhancement circuit 6 of a D/A converter adopting the DWA scheme. The linearity enhancement circuit 6 has an A/D converter 7 disposed on its input side and a D/A converter 8 on its output side. FIG. 3 shows a case involving the use of a three-bit A/D converter 7 that is a flash type with thermometer code used as its output code.
The linearity enhancement circuit 6 is made up of a conversion circuit 61 for converting thermometer code into binary code, an adder 62, flip-flop circuits 63 and 64, and a shifter circuit 65 for bit-shifting thermometer code. In the linearity enhancement circuit 6, the code bit-shifted by the shifter circuit 65 is always rotated as shown in FIG. 4. The rotated code causes the D/A converter 8 to act in a manner implementing the workings of FIG. 2B.
Typical structures of the circuit in FIG. 3 are described illustratively in Japanese Patent Laid-Open No. 2006-262488 (U.S. Pat. No. 4,195,040; called Patent Document 1 hereunder); in “A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless LAN Receivers,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 2, February 2006 (called Non-Patent Document 1 hereunder); and in “A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, February 2008 (called Non-Patent Document 2 hereunder).